Optimized version:

9.11.3. Pad Control - User Bank

9.6. Pads

Each GPIO is connected off-chip via a pad. Pads are the electrical interface between the chip’s internal logic and external circuitry. They translate signal voltage levels, support higher currents and offer some protection against electrostatic discharge (ESD) events. You can adjust pad electrical behaviour to meet the requirements of external circuitry in the following ways: • Output drive strength can be set to 2mA, 4mA, 8mA or 12mA. • Output slew rate can be set to slow or fast. • Input hysteresis (Schmitt trigger mode) can be enabled. • A pull-up or pull-down can be enabled, to set the output signal level when the output driver is disabled. • The input buffer can be disabled, to reduce current consumption when the pad is unused, unconnected or connected to an analogue signal. An e

RP2350 has isolation latches on all GPIO (RP2040 only on some). We need to enable the pad input (GPIO0.IE = 1) and disable pad isolation latches (GPIO0.ISO = 0) before using the pads for digital I/O. If the SDK is used this is done with the function gpio_set_function().

Pad isolation is needed for extended low-power states. More info in chapter 9.7. (Pad isolation latches) in the RP2350 data sheet.

Core-local Peripherals (SIO)

3.1.11. List of registers

The SIO registers start at a base address of 0xd0000000 (defined as SIO_BASE in SDK).

Table 17. List of SIO registers Table 21. GPIO_OUT register Set output level (1/0 → high/low)

9.8. Processor GPIO controls (SIO) (Section 3.1) contains memory-mapped GPIO registers. The processors can use these to perform input/output operations on GPIOs: • The GPIO_OUT and GPIO_HI_OUT registers set the output level: 1 = high, 0 = low • The GPIO_OE and GPIO_HI_OE registers set the output enable: 1 = output, 0 = input • The GPIO_IN and GPIO_HI_IN registers read the GPIO inputs These registers are all 32 bits in size. The low registers (e.g. GPIO_OUT) connect to GPIOs 0 through 31, and the high registers (e.g. GPIO_HI_OUT) connect to GPIOs 32 through 47, the QSPI pads, and the USB DM/DP pads. For the output and output enable registers to take effect, the SIO function must be selected on each GPIO (function 5). However, the GPIO input registers read back the GPIO input values even when the SIO function is not selected, so the processor can always check the input state of any pin. The SIO GPIO registers are shared between the two processors and between the Secure and Non-secure security domains. This avoids programming errors introduced by selecting multiple GPIO functions for access from different contexts. Non-secure code’s view of the SIO registers is restricted by the Non-secure GPIO mask defined in GPIO_NSMASK0 and GPIO_NSMASK1. Non-secure writes to Secure GPIOs are ignored. Non-secure reads of Secure GPIOs return 0. These registers are documented in more detail in the SIO GPIO register section (Section 3.1.3). The DMA cannot access registers in the SIO subsystem. The recommended method to DMA to GPIOs is a PIO program that continuously transfers TX FIFO data to the GPIO outputs, which provides more consistent timing than DMA directly into GPIO registers

Download rars1_6.jar from https://github.com/TheThirdOne/rars/releases/tag/v1.6 java -jar -Dsun.java2d.uiScale=2.0 ./rars1_6.jar

The GPIO_OUT_SET register is designed for atomic bit setting—writing a 1 to any bit sets that bit in the GPIO output register without read-modify-write overhead.

Single Instruction:

Only 1 sw instruction is needed to set the bit. No lw (load) or RMW (read-modify-write) overhead.

Atomic Operation:

The hardware guarantees atomicity—no risk of race conditions.

No Stalls: The sw instruction completes in 1 cycle (assuming no memory contention).

| code | cycles | comment | |--|--| |loop: || | li t0, GPIO_OUT # Load the address of the GPIO output register|| | lw t1, 0(t0) # Load the current value of the GPIO output register|| | li t2, GPIO_MASK # Load the bitmask for GPIO|| | or t1, t1, t2 # Set the bit for our GPIO (turn OUTPUT on)|| | sw t1, 0(t0) # Store the updated value back to the GPIO output reg.|| | li t0, GPIO_OUT # Load the address of the GPIO output register|| | lw t1, 0(t0) # Load the current value of the GPIO output register|| | li t3, ~GPIO_MASK # Load the bitmask for GPIO|| | and t1, t1, t3 # Clear the bit for GPIO (turn OUTPUT off)|| | sw t1, 0(t0) # Store the updated value back to the GPIO output reg.|| | j loop # Jump back to the start of the loop (infinite loop)||

| code | cycles | |--|--| li t0, GPIO_OUT # Load the address of the GPIO output register li t2, GPIO_MASK # Load the bitmask for GPIO li t3, ~GPIO_MASK # Load the bitmask for GPIO |loop: || lw t1, 0(t0) # Load the current value of the GPIO output register or t1, t1, t2 # Set the bit for our GPIO (turn OUTPUT on) sw t1, 0(t0) # Store the updated value back to the GPIO output reg. lw t1, 0(t0) # Load the current value of the GPIO output register and t1, t1, t3 # Clear the bit for GPIO (turn OUTPUT off) sw t1, 0(t0) # Store the updated value back to the GPIO output reg. j loop # Jump back to the start of the loop (infinite loop)

The tight loop in the code consists of 3 instructions:

toggle_loop: li t0, GPIO_OUT_XOR | 2 | pseudo-instruction, expands to addi | li t1, (1 << 15) | 2 | pseudo-instruction, expands to addi | sw t1, 0(t0) | 1 | Store Word to GPIO_XOR (assuming no stalls) | j toggle_loop | 1 | branch prediction helps here | | | Total per iteration | 6 | |

590ns/6 = 98,33ns = 10,169MHz

From the data sheet (8.3. Ring oscillator (ROSC)): <quote>The Ring Oscillator (ROSC) is an on-chip oscillator built from a ring of inverters. It requires no external components and is started automatically during RP2350 power up. It provides the clock to the cores during boot. During boot, the ROSC runs at a nominal 11MHz and is guaranteed to be in the range 4.6MHz to 19.6MHz without randomisation…​</quote>