Microcontroller projects

mkdir -p ~/pi_pico2/risc_v_gcc
cd ~/pi_pico2/risc_v_gcc
wget https://buildbot.embecosm.com/job/corev-gcc-ubuntu2204/83/artifact/corev-openhw-gcc-ubuntu2204-20250302.tar.gz
tar -xzf corev-openhw-gcc-ubuntu2204-20250302.tar.gz

cd ~/pi_pico2/risc_v_gcc/corev-openhw-gcc-ubuntu2204-20250302/bin/
riscv32-corev-elf-gcc --version

export PATH="$PATH:/home/weigu/pi_pico2/risc_v_gcc/corev-openhw-gcc-ubuntu2204-20250302/bin"

### Toggle an GPIO pin (minimal version)
### 01_toggle.S
### weigu.lu

    ### RP2350 Image Definition Block
    # This block is required for the RP2350 to recognize the binary as a valid
    # RISC-V executable. It must appear within the first 4 KB of the image.
    # RP2350 data sheet: 5.9.1. Blocks and block loops
    # 5.9.3. Image definition items, 5.9.3.4. ENTRY_POINT item
    .p2align 8       # Align to 8-byte boundary (required for RP2350 image header)
    .word 0xffffded3 # Header magic number (identifies the image)
    .word 0x11010142 # Item 0 flags: 0b0001 0001 0000 0001 0000 0100 0010
             # IMAGE_TYPE_EXE, EXE_SECURITY_UNSPECIFIED,
             # EXE_CPU_RISC,  EXE_CHIP_RP2350
    .word 0x00000344 # Item 1: Block size = 3,
             # Block type = PICOBIN_BLOCK_ITEM_1BS_ENTRY_POINT
    .word _start     # Item 2: Inital PC (runtime) address (aka entry point)
    .word _stack_top # Item 3: Initial SP address (aka stack pointer)
    .word 0x000004ff # Item 4: Optional SP limit address (aka stack limit)
    .word 0x00000000 # Link: Single block loop has 0 items
    .word 0xab123579 # Footer magic number

    .section .text          # Marks the start of the code section in memory
    .global _start          # Makes the symbol '_start' visible to the linker

    ### Pin to use
    .equ PIN_OUT, 15
    .equ GPIO_MASK,       (1 << PIN_OUT)    # Bitmask for GPIO (e.g. GPIO15 = bit 15)
    .equ GPIO_OFFSET,     PIN_OUT*8+4   # Offset for GPIO reg. (+0 = Status, +4 = Ctrl)
    .equ PADS_OFFSET,     PIN_OUT*4+4   # Offset for PAD reg. (GPIO0 starts with +4)
    .equ DELAY_NUMBER,    1000000       # 1000000 gives us about 2 Hz (12MHz clock)


    ### Memory-Mapped Register Definitions
    .equ IO_BANK0_BASE,   0x40028000    # IO Bank0 Base Address
    .equ GPIO_CTRL,       IO_BANK0_BASE + GPIO_OFFSET # GPIO_CTRL register (for Mux)
    .equ SIO_BASE,        0xD0000000    # SIO (Single-Cycle I/O) Base Address
    .equ GPIO_OUT_XOR,    SIO_BASE + 0x28   # GPIO output XOR register (atomic)
    .equ GPIO_DIR,        SIO_BASE + 0x30   # GPIO direction register
    .equ PADS_BANK0_BASE, 0x40038000    # User Bank Pad Control register base
    .equ PAD,             PADS_BANK0_BASE + PADS_OFFSET # PADS_BANK0: PIN_OUT register

### Entry Point: _start
_start:     la sp, _stack_top   # Load the stack pointer with the top of the stack
        call main       # Call the main function
        wfi         # Wait for interrupt (low-power mode)
        j _start        # Infinite loop (should never reach here)


### Main Function
    .section .text          # Code section
    .global main            # Make 'main' visible to the linker

main:
        # SETUP: Tell the multiplexer to set our Pin to GPIO
        li t0, GPIO_CTRL    # Load the address of the GPIO_CTRL register to t0
        lw t1, 0(t0)        # Load the current value of the GPIO_CTRL register to t1
        andi t1, t1, ~0x1F  # Clear the lower 5 bits (function select)
        ori t1, t1, 5       # Set the function select to 5 (GPIO mode)
        sw t1, 0(t0)        # Store the updated value back to the GPIO_CTRL reg.

        ### SETUP: Set GPIO15 as an output
        li t0, GPIO_DIR     # Load the address of the GPIO direction register
        lw t1, 0(t0)        # Load the current value of the direction reg. to t1
        li t2, GPIO_MASK    # Load the bitmask for the used GPIO
        or t1, t1, t2       # Set the bit for used GPIO (output mode)
        sw t1, 0(t0)        # Store the updated value back to the GPIO dir. reg.

        ### Setup: Clear Pad Isolation for GPIO
        li t0, PAD      # Load the address of the pad register
        lw t1, 0(t0)        # Load the current value of the pad register
        andi t1, t1, ~0x100 # Clear isolation bit (bit nr 8)
        ori t1, t1, 0x30    # Drive strength 12mA
        sw t1, 0(t0)        # Store the updated value back to the pad register

        li t0, GPIO_OUT_XOR # Load the address of the GPIO_OUT_XOR
        li t1, GPIO_MASK    # Load the bit for the output GPIO to be toggled

mainloop:   # Main Loop: Toggle output on GPIOx
        sw t1, 0(t0)        # Set the bit (atomic bit setting-writing)
        #li a0, DELAY_NUMBER     # set counter for delay loop (parameter a0)
        #jal delay      # jump and link delay (command call bor big jumps)
        j mainloop      # jump mainloop forever

delay:      # Subroutine delay (parameter a0)
        addi a0, a0, -1     # decrement a0
                bnez a0, delay      # stay in loop until counter = 0
                ret

mkdir -p ~/pi_pico2/pico2_riscv_ass/01_toggle
cd ~/pi_pico2/pico2_riscv_ass/01_toggle
nano 01_toggle.S

OUTPUT_ARCH(riscv)
ENTRY(_start)
MEMORY {
    FLASH (rx)  : ORIGIN = 0x10000000, LENGTH = 2M
    RAM   (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
}
SECTIONS {
    .text : {
        *(.text*)
    } > FLASH

    .data : {
        *(.data*)
    } > RAM

    .bss : {
        *(.bss*)
    } > RAM

    .stack (NOLOAD) : {
        . = ALIGN(8);
        _stack_top = . + 4K; /* 4KB stack */
    } > RAM
}

nano linker.ld

#!/bin/bash
if [ "$#" -ne 1 ]; then
    printf 'ERROR! You must provide one and only one argument!\n' >&2
    exit 1
fi
riscv32-corev-elf-as -g -march=rv32imac -mabi=ilp32 -o $1.o $1.S
riscv32-corev-elf-ld -g -m elf32lriscv -T linker.ld -o $1.elf $1.o
riscv32-corev-elf-objcopy -O binary $1.elf $1.bin
riscv32-corev-elf-objdump -f $1.elf
openocd -f interface/cmsis-dap.cfg -f target/rp2350-riscv.cfg -c "adapter speed 5000" \
-c "program blink.elf verify reset exit"

nano ass_link_program.sh

chmod u+x ass_link_program.sh
./ass_link_program.sh blink